This invention relates to semiconductor memory devices and more particularly to an MOS ROM which is electrically programmable and electrically erasable.
Electrically programmable memory devices have been developed as shown in U.S. Pat. No. 3,984,822 which employ a floating gate in a double level polysilicon MOS ROM; for programming, the floating gate is charged by injection of electrons from the channel. Generally, however, this floating gate EPROM device is erased by exposing to ultraviolet light. Electrically erasable devices of MNOS type have employed charge storage on a nitride-oxide interface. Electrically alterable ROM's have been developed as set forth in U.S. Pat. No. 3,881,180, issued Apr. 29, 1975, and 3,882,469, issued May 6, 1975, as well as application Ser. No. 644,982, filed Dec. 29, 1975, all by W. M. Gosney and assigned to Texas Instruments; the Gosney devices are floating gate cells with dual injection (both holes and electrons) so that the gates may be charged or discharged. Other electrically alterable EPROM's are disclosed in U.S. Pat. Nos. 4,122,509 and 4,122,544 by Lawrence S. Wall or David J. McElroy, assigned to Texas Instruments. However, the prior cells have exhibited some undesirable characteristics such as large cell size, complex structure, process instability, process incompatible with standard techniques, high voltages needed for programming of erasure, etc.
It is therefore the principal object of the invention to provide improved electrically erasable semiconductor devices e.g., electrically alterable, programmable read-only-memory cells. Another object is to provide an electrically erasable memory cell which is of small cell size when formed in a semiconductor integrated circuit, particularly a dual injection type cell. A further object is to provide dense arrays of electrically erasable memory cells generally compatible with N-channel floating gate EPROM technology.